Multichip modules provide a plurality of functional wafers which are supported and interconnected on a single substrate, and thereafter the module may be connected to other components as an integral unit.
As compared to integrated circuits, the multichip module provides opportunity for use of various incompatible technologies (i.e., those that cannot be fabricated together) within a single system component, and the use of relatively simpler components and lower spatial density than required within an integrated circuit to obtain the same functionality. However, by eliminating separate packaging for the components, certain costs can be reduced, density increased, and performance increased with respect to discrete packaged or wire-bonded components on a circuit board.
In normal semiconductor technology circuits, operation leads to significant heat dissipation, and when such components are supported in a multichip module, potentially significant amounts of heat must be removed through the module substrate and packaging. Therefore, the interface between the functional wafer and substrate for such modules should have a low thermal impedance (high thermal conductivity). For example, a low melting temperature alloy may be used to both electrically and mechanically bond the wafer to the substrate through a set of “solder bumps”. This process typically requires heating the substrate and wafer above the reflow temperature of the solder, and thus may damage certain temperature-sensitive electronics. Because of thermal cycling issues, the wafer and substrate should have matching thermal coefficients of expansion. Typically, there is no filler material between the wafer and substrate prior to reflow, since this could impair the reflow process or cause other problems. A filler may be added in the space between the wafer and substrate after reflow, for example to enhance thermal conductivity.
Superconducting circuits based on Rapid-Single-Flux-Quantum logic are the fastest in any electronic technology, with clock speeds in excess of 20 GHz routinely achieved, and speeds in excess of 100 GHz projected as the devices are scaled to smaller sizes. In the preferred embodiment of these integrated circuits, they are composed of thousands of Josephson junctions, each constructed from two layers of superconducting niobium with an intervening oxide layer about 1 nanometer thick. To function properly, these circuits must be cooled to cryogenic temperatures below the critical temperature of 9 K (−264 C). Further, the very thin oxide layer of the circuits can be damaged by temperatures in excess of about +200 C, so elevated temperatures in fabrication and processing must be avoided. This is a low-power, low-voltage, low-impedance technology, based on the propagation of voltage pulses less than 1 mV high and 1 picosecond wide, with device resistances of a few ohms. As the technology has developed, it has become necessary to develop multi-chip modules (MCM), where these fast voltage pulses pass between superconducting chips on a superconducting carrier. To be practical, such an MCM must be both robust and reliable for all high-speed links in the package.
Superconducting circuits as currently implemented typically have a lower functional density than their more evolved silicon semiconductor counterparts, and therefore achieving complex functionality may require multiple wafers. Superconducting circuits dissipate small amounts of power, and therefore the function of the substrate is principally to provide mechanical support and electrical pathways, and far less to provide effective dissipation of operating power. During cooldown to cryogenic temperatures, the MCM is typically mounted in a vacuum, and therefore the thermal path for cooling is generally through the supporting substrate.
A standard technique for superconducting MCMs has been developed in the prior art, based on indium-tin solder reflow. The In—Sn alloy was chosen since it melts at a very low temperature, less than 200 C. First, a superconducting chip with gold contacts is dipped in a bath of molten solder, and In—Sn droplets attach to the gold contacts and cool to form solid bumps. The chip is then carefully aligned so that these solder bumps are directly above corresponding gold contacts in the chip carrier. Then, the assembly is carefully heated to remelt the solder bumps, which then flow to wet the gold contacts on the carrier (“solder reflow”). The assembly is then clamped and cooled down to room temperature. The resulting MCM is then mounted in a cryogenic package and cooled to below 9 K for high-speed testing. Devices made in this way have demonstrated transmission of high-speed pulses up to about 100 GHz. K. E. Yokoyama, G. Akerling, A. D. Smith, and M. Wire, “Robust Superconducting Die Attach Process”, IEEE Trans. Applied Supercond., VOL. 7, NO. 2 (June 1997), pp. 2631-2634, describes In—Sn reflow (<140C) solder bonds for superconducting MCMs using flip chip technology, i.e., a controlled collapse micro-solder reflow technique. See also, U.S. Pat. No. 5,920,464, (Reworkable microelectronic multi-chip module, Yokoyama); 6,032,852 (Reworkable microelectronic multi-chip module, Yokoyama), 6,050,476 (Reworkable microelectronic multi-chip module, Yokoyama), 6,216,941 (Method for forming high frequency connections to high temperature superconducting circuits, Yokoyama), each of which is expressly incorporated herein by reference. However, the existing techniques for die attachment for superconducting MCMs, including Yokoyama et al., are not adequate for the demanding ambient conditions these systems must endure. For example, modules constructed using the reflow technique according to Yokoyama et al. tend to fail under vibration, and especially ultrasonic vibration. The reliability of the bond achieved by the In—Sn solder-reflow method is very weak, with poor adhesion, and the contacts break easily with thermal cycling and handling. Furthermore, the necessary wetting during the reflow process becomes less reliable as the contact area decreases, particularly for sizes of 50 microns or less. This is unacceptable for packaging of chips with many small contacts.
When using superconducting electronics, the ability to support high data rate communications, both within a wafer, and between wafers, is critical. For example, a target specification is to provide clock and data links between receiver front ends and subsequent digital signal processing circuits at rates above 40 Gbps. Such systems find application in high bandwidth communications systems and processing circuits, which may require location in the field using a cryocooler, where environmental stresses are apparent. Thus, an improved multichip module fabrication technique with improved vibrational tolerance is desired.
Differential thermal expansion is well known to create problems in stressing glued connections. See, Hsieh (U.S. Pat. No. 6,605,491), expressly incorporated herein by reference, which discusses bonding a silicon chip to a polymeric substrate, and in particular thermal stress issues over a range of −55 C and +125 C, using adhesives generally having a high viscosity. Such thermal stress can cause bowing in flexible substrates, and flaking or cracking of the adhesive in rigid substrates. See also, U.S. Pat. No. 6,919,642. These problems would be much worse for temperature variations from above room temperature to near absolute zero, a range of over 300K. It is also well known that many materials (especially most polymers) become weak and brittle at cryogenic temperatures.
U.S. App. 20040214377 and EP 1,473,769 entitled “Low thermal expansion adhesives and encapsulants for cryogenic and high power density electronic and photonic device assembly and packaging”, expressly incorporated herein by reference, adhesives, with a high viscosity, for bonding electronic device in which small particles with a negative coefficient of thermal expansion (CTE) are added to produce a filled adhesive with small net CTE to match the wafers to be bonded, in order to prevent delamination due to stress at cryogenic temperatures.